The present invention relates to a circuit configuration and also a method for accelerating aging in an MRAM (Magnetoresistive Memory). The MRAM has a memory cell array in which a multiplicity of memory cells, each having a soft-magnetic layer and a hard-magnetic layer, are configured at crossover points between two control lines into which control signals can be fed via a respective first control unit.
As is known, MRAM cells include a soft-magnetic layer, a tunneling barrier layer and a hard-magnetic layer, which are stacked between two mutually crossing control lines, namely at the crossover point of a word line and a bit line. In normal operation, such MRAM cells are written to by means of superposed magnetic fields which are generated by currents flowing through the control lines. In this case, the hard-magnetic layer maintains its magnetization direction, while in the soft-magnetic layer, the magnetization direction is set depending on the direction of the currents flowing in the control lines and, if appropriate, the magnetization direction is flipped over. In the case of mutually parallel magnetization directions in the hard-magnetic layer and the soft-magnetic layer, the MRAM cell has a lower resistance, while in the case of anti-parallel magnetization directions in these layers, a higher-resistance is present. This lower or higher electrical resistance can then be evaluated as an information unit xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, or vice versa.
It has now been shown that MRAM cells are subject to an aging process. Thus, after a period of ten years, for example, or after repeated access in a number of 1012, for example, to one and the same MRAM cell, the latter is aged, which can be manifested in that the magnetization direction or polarization of the soft-magnetic layer is no longer exactly parallel or As anti-parallel with respect to the magnetization direction or polarization of the hard-magnetic layer. However, if this parallelism or anti-parallelism of the magnetization directions in the soft-magnetic layer and the hard-magnetic layer is no longer given, then there is inevitably a decrease in the read signal since it is no longer possible to reliably distinguish between the two states of parallel magnetization and anti-parallel magnetization. Ultimately, this can cause a failure of the MRAM.
Since memory cells can age differently, knowledge of the progression of the aging process in an MRAM is of great importance. However, the examination of such an aging process is extremely costly since, for the aging, either it is necessary to wait for a very long time, which is unacceptable in view of a period of about ten years, or it is necessary to perform a large number of repeated accesses in a high multiple of 1012, which requires a not inconsiderable outlay with respect to time and apparatus.
It is accordingly an object of the invention to provide a circuit configuration and a method for accelerating aging which overcomes the above-mentioned disadvantageous of the prior art configurations and methods of this general type. In particular, it is an object of the invention to provide a circuit configuration and a method for accelerating aging that can implement aging with a lower outlay than that required in the prior art.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for accelerating aging in an MRAM. The circuit configuration includes an MRAM having: a plurality of control lines that cross one another at locations defining crossover points; a memory cell array with a plurality of memory cells, one of the plurality of the memory cells located at a respective one of the crossover points at which two of the plurality of the control lines crossover, the two of the plurality of the control lines that cross over defining two control lines, the one of the plurality of the memory cells including a soft-magnetic layer and a hard-magnetic layer; and a first control unit for feeding a current forming a control signal into a respective one of the two control lines. The circuit configuration also includes a second control unit connected in parallel with the first control unit. The second control unit is for feeding a current, into the respective one to of the two control lines, which is larger than the current fed in by the first control unit.
In accordance with an added feature of the invention, the respective one of the two control lines is located closer to the soft-magnetic layer than another one of the two of the control lines; and the second control unit is connected to the respective one of the two of the control lines.
In accordance with an additional feature of the invention, the second control unit includes a driver transistor.
In accordance with another feature of the invention, the first control unit includes two driver transistors connected in series.
In accordance with a further feature of the invention, the second control unit includes a first driver transistor connected in parallel with one of the two driver transistors of the first control unit; and the second control unit includes a second driver transistor connected in parallel with another one of the two driver transistors of the first control unit.
In accordance with a further added feature of the invention, to the two driver transistors of the first control unit, the first transistor of the second control unit, and the second transistor of the second control unit all have the same conduction type.
The objects of the invention are achieved by virtue of the fact that a second control unit is additionally provided in parallel with the first control unit. The second control unit enables a larger current to be fed into the associated control line than with the first control unit.
As a second control unit, a second transistor is inserted in parallel with the driver transistors, which form the first control unit. The second transistor supplies a current through the control line located nearer the soft-magnetic layer. The second transistor can drive a higher current through the control line and can be activated by means of a test mode.
This higher current effects hard switching of the soft-magnetic layer, i.e. the soft-magnetic layer changes its polarization even without superposition of a magnetic field through a current in the other control line. It is thus possible, for the purpose of reducing power, to switch off driver transistors which form the control unit of the control line located nearer the hard-magnetic layer. The hard switching in the test mode by means of the higher current through the second control unit also degrades the hard-magnetic layer and brings about a reduction in the read signal, i.e. aging of the memory cell.
Thus, with the introduction of a test mode, the invention enables a hard switching which makes it possible to achieve accelerated aging of the memory cell.
Since memory cells are damaged by this aging, the invention is particularly suitable for application in monitor cells in a special memory cell array formed by the latter.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for accelerating aging in an MRAM, that includes providing an MRAM having: a plurality of control lines that cross one another at locations defining crossover points; a memory cell array with a plurality of memory cells, one of the plurality of the memory cells located at a respective one of the crossover points at which two of the plurality of the control lines crossover, the two of the plurality of the control lines that cross over defining two control lines, the one of the plurality of the memory cells including a soft-magnetic layer and a hard-magnetic layer; and a first control unit for feeding a current forming a control signal into a respective one of the two control lines. The method also includes steps of locating the respective one of the two control lines closer to the soft-magnetic layer than another one of the two of the control lines; and feeding a current, which has a higher magnitude than that used during a normal read/write operation, into the respective one of the two control lines that is closer to the soft-magnetic layer.
The method is distinguished by the fact that a higher current than during normal reading/writing is fed into the control line located nearer the soft-magnetic layer, and that the other control line, which is located nearer the hard-magnetic layer, is switched off.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration and method for accelerating aging in an mram, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.